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IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVC162268
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA (A port) * Balanced Output Drivers: 12mA (B port)
* 3.3V high speed systems * 3.3V and lower voltage computing systems
This registered bus exchanger is built using advanced dual metal CMOS technology. This device is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The ALVC162268 device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-tohigh transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). These control terminals are registered to synchronize the bus-direction changes with CLK. The ALVC162268 has series resistors in the device output structure of the "B" port which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. The "A" port has a 24mA driver.
FUNCTIONAL BLOCK DIAGRAM
CLK
29
2
CLKEN1B
27
CLKEN2B
30
CLKENA1
CLKENA2 OEB
55
C1
56
1D C1
SEL O EA
28
1D
1
1D C1
CE C1 1D
23
1B 1
A1
8
0 1
CE C1 1D
6
2B 1
CE C1 1D
CE C1 1D
CE C1 1D 1 of 12 Channels
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4550/1
IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEA CLKEN1B
2B 3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OEB CLKENA2
2B 4
Unit V V C mA mA mA mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
2B 2 2B 1
GND
2B 5 2B 6
VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC
1B 1 1B 2
VCC
2B 7 2B 8 2B 9
GND
2B 10 2B 11 2B 12 1B 12 1B 11 1B 10
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
GND
1B 9 1B 8 1B 7
NOTE: 1. As applicable to the device type.
VCC
1B 6 1B 5
FUNCTION TABLES(1)
OUTPUT ENABLE
Inputs CLK OEA H H L L OEB H L H L Ax Z Z Active Active Outputs 1Bx, 2Bx Z Active Z Active
GND
1B 3
GN D
1B 4
C LKEN2B SEL
CLKENA1 CLK
SSOP/ TSSOP/ TVSOP TOP VIEW
A-TO-B STORAGE (OEB = L AND OEA = H)
Inputs CLKENA1 H L L X X CLKENA2 H L L L L CLK X Ax X L H L H Outputs 1Bx
(2) 1B0 (3) (3)
2Bx 2B0 L H L H
(2)
L
H
X X
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IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLES (CONTINUED)(1)
B-TO-A STORAGE (OEA = L AND OEA = H)
Inputs CLKEN1B H X L L X X CLKEN2B X H X X L L CLK X X SEL H L H H L L 1Bx X X L H X X 2Bx X X X X L H Output Ax A0 A0
(2) (2)
L H L H
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 3. Two CLK edges are needed to propagate data.
PIN DESCRIPTION
Pin Names Ax (1:12) 1Bx (1:12) 2Bx (1:12) CLK CLKENA1 CLKENA2 CLKEN1B CLKEN2B SEL OEA OEB I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's address/data bus. Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory. Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory. Clock Input Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). Clock Enable Input for the A-1B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). Clock Enable Input for the A-1B Register. If CLKEN1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). Clock Enable Input for the A-1B Register. If CLKEN2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). 1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port (Active LOW). Synchronous Output Enable for A Port (Active LOW) Synchronous Output Enable for A Port (Active LOW)
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IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 4mA IOH = - 6mA IOH = - 4mA IOH = - 8mA IOH = - 6mA IOH = - 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC - 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 87 80 VCC = 3.3V 0.3V Typical 120 118 Unit pF
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IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS (A PORT)(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tSU tSU tSU tH tH tH tH tW tSK(O) Propagation Delay CLK to Ax (1B) Propagation Delay CLK to Ax (2B) Propagation Delay CLK to Ax (SEL) Output Enable Time CLK to Ax Output Disable Time CLK to Ax Set-up Time, Ax data before CLK Set-up Time, SEL before CLK Set-up Time, CLKENA1 or CLKENA2 before CLK Set-up Time, OEA before CLK Hold Time, Ax data after CLK Hold Time, SEL after CLK Hold Time, CLKENA1 or CLKENA2 after CLK Hold Time, OEA after CLK Pulse Width, CLK HIGH or LOW Output Skew(2) 4.5 1.4 3.6 4.2 0 1 0.1 0 3.3 -- -- -- -- -- -- -- -- -- -- -- 4 1.6 3.4 3.9 0 1 0.1 0 3.3 -- -- -- -- -- -- -- -- -- -- -- 3.4 1.3 2.8 3.2 0.2 1 0.4 0.2 3.3 -- -- -- -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ns ns ns ps 2 6.5 -- 5.4 2.1 5 ns 2 6.2 -- 5.6 1.8 5.1 ns 2.5 7.3 -- 6.5 2.4 5.8 ns 1.6 5.8 -- 5.3 1.8 4.8 ns Parameter Min. 120 1.6 Max. -- 5.8 VCC = 2.7V Min. 125 -- Max. -- 5.4 VCC = 3.3V 0.3V Min. 150 1.7 Max. -- 4.8 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS (B PORT)(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tSU tSU tH tH tH tSK(O) Propagation Delay CLK to 1Bx, 2Bx Output Enable Time CLK to 1Bx, 2Bx Output Disable Time CLK to 1Bx, 2Bx Set-up Time, Bx data before CLK Set-up Time, CLKEN1B or CLKEN2B before CLK Set-up Time, OEB before CLK Hold Time, Bx data after CLK Hold Time, CLKEN1B or CLKEN2B after CLK Hold Time, OEB after CLK Output Skew(2) 0.8 3.2 4.2 1.3 0.1 0 -- -- -- -- -- -- -- -- 1.2 3 3.9 1.2 0 0 -- -- -- -- -- -- -- -- 1 2.5 3.2 1.3 0.5 0.2 -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ps 2.8 7.2 -- 6.1 2.5 5.9 ns 2.7 7.2 -- 6.8 2.6 6.1 ns Parameter Min. 120 1.6 Max. -- 6.1 VCC = 2.7V Min. 125 -- Max. -- 5.9 VCC = 3.3V 0.3V Min. 150 1.8 Max. -- 5.4 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
ALV C Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse Generator
(1, 2)
SAME PHASE INPU T TRAN SITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OU TPUT tPLH OPPOSITE PHASE INPU T TRAN SITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CON TROL IN PUT tPZL
DISABLE
VIN D .U .T.
VOUT
VIH VT 0V VLOAD/2 VOL + VLZ VOL VOH VOH - VHZ 0V
ALV C Link
tPLZ VLOAD/2 VT tPHZ VT 0V
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
OUTPU T SW ITCH NOR MALLY CLO SED LOW tPZH OU TPUT SW ITCH NORMALLY O PE N H IGH
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH INPU T VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2
ALVC Link
DATA INPUT TIMING INPU T ASYNC HRON OU S CON TROL SYNC HRON OU S CON TROL
tSU
tH
tREM
tSU
tH
Set-up, Hold, and Release Times
tPLH1
tPHL1
LOW -H IGH -LOW PULSE tW HIGH-LOW -HIGH PULSE
VT
tSK (x)
tSK (x)
VT
ALVC Link
VT VOL
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVC162268 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX ALVC X Bus-Hold XX Fam ily XXX Device Type XX Package Temp. Range
PV PA PF 268 162
Shrink Small Outline P ackage Thin Shrink Small Outline Package Thin Very Sm all Outline Package 12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs Double-Density, 24m A (A port) 12m A (B port) No Bus-Hold -40C to +85C
Blank 74
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